1. Field of the Invention
The invention relates to the process of verifying a design for an integrated circuit. More specifically, the invention relates to a method and an apparatus for integrating a simulation log, which is generated during simulation of the design, into a verification environment.
2. Related Art
During the design of an integrated circuit, designers typically use a high-level hardware design language such as Verilog or VHDL to create a register transfer language (RTL) description of the integrated circuit.
The RTL description is typically processed through a simulator to verify correct operation of the design. During this simulation, the simulator writes messages containing information generated during the simulation to a log file. These messages typically contain information related to key events which occur during the simulation run. Designers use this log file to review the operation of the integrated circuit design.
During a review of the log file (either during the simulation run or during post-processing of the simulation run), the designer typically locates an entry for an event of interest in the log file and attempts to correlate this entry with other files associated with the simulation. These other files can include: the RTL source, hierarchical views of circuits within the integrated circuit, and circuit waveforms generated during the simulation.
Unfortunately, in existing systems, the process of associating the entry in the log file to specific locations in the other files is a time-consuming manual process. Furthermore, because this process is manual, it is prone to errors, such as associating a log file entry with the wrong circuit, or associating a log file entry with the wrong portion of a waveform.
Hence, what is needed is a method and an apparatus for integrating a simulation log into a verification environment without the problems cited above.